smc_peripherals_cdc
Cross SMC and peripheral clock domains for peripheral control and status.
Carries the AVSBus, I2C, UART and I3C AXI-Lite register paths from the SMC clock to the peripheral clock and the log-engine fetch path back, each through an axi_cdc. Flops and synchronizes enables, interrupts and debug status into the SMC clock, and clock-gate enables from the SMC clock into the ungated peripheral, reference and telemetry clocks. The level synchronizers have no reset.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
SYNC_STAGES | int unsigned | 3 | Synchronizer depth of the AXI-Lite CDCs and the level synchronizers, 2 or 3; any other value is fatal. The NDM reset synchronizer always uses 3. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_smc_i | input | logic | SMC core clock. |
clk_periph_i | input | logic | Ungated peripheral clock. |
clk_ref_i | input | logic | Ungated reference clock; destination of the AVSBus reference-clock gate enable. |
clk_telemetry_i | input | logic | Ungated telemetry clock; destination of the telemetry clock-gate enable. |
rst_smc_clk_ni | input | logic | Reset of the SMC-clock side of the AXI-Lite CDCs and the AVSBus state synchronizer, active-low, synchronized to clk_smc_i. |
rst_periph_clk_ni | input | logic | Reset of the peripheral-clock side of the AXI-Lite CDCs and the AVSBus state synchronizer, active-low, synchronized to clk_periph_i. |
axil_avsbus_req_smc_clk_i | input | smc_pkg::smc_axil_32_32_req_t | AVSBus register request from the SMC-clock crossbar. |
axil_avsbus_resp_smc_clk_o | output | smc_pkg::smc_axil_32_32_resp_t | AVSBus register response to the SMC-clock crossbar. |
axil_avsbus_req_periph_clk_o | output | smc_pkg::smc_axil_32_32_req_t | AVSBus register request to the controller on the peripheral clock. |
axil_avsbus_resp_periph_clk_i | input | smc_pkg::smc_axil_32_32_resp_t | AVSBus register response from the controller on the peripheral clock. |
axil_i2c_req_smc_clk_i | input | smc_pkg::smc_axil_32_32_req_t | I2C register request from the SMC-clock crossbar. |
axil_i2c_resp_smc_clk_o | output | smc_pkg::smc_axil_32_32_resp_t | I2C register response to the SMC-clock crossbar. |
axil_i2c_req_periph_clk_o | output | smc_pkg::smc_axil_32_32_req_t | I2C register request to i2c_wrap on the peripheral clock. |
axil_i2c_resp_periph_clk_i | input | smc_pkg::smc_axil_32_32_resp_t | I2C register response from i2c_wrap on the peripheral clock. |
i2c_enable_smc_clk_o | output | logic [smc_config_pkg::NumI2c-1:0] | Per-instance I2C enable synchronized to clk_smc_i. |
i2c_enable_periph_clk_i | input | logic [smc_config_pkg::NumI2c-1:0] | Per-instance I2C enable from i2c_wrap on the peripheral clock. |
i2c_irqs_smc_clk_o | output | logic [smc_config_pkg::NumI2c-1:0] | Per-instance I2C interrupt synchronized to clk_smc_i. |
i2c_irqs_periph_clk_i | input | logic [smc_config_pkg::NumI2c-1:0] | Per-instance I2C interrupt on the peripheral clock. |
i2c_debug_periph_clk_i | input | logic [smc_config_pkg::NumI2c-1:0][3:0] | I2C Debug Bus CDC (Periph -> SMC). Visibility-only path consumed by the SMC debug bus mux. Per-bit sync is acceptable; coherency across bits is not required for debug observation. |
i2c_debug_smc_clk_o | output | logic [smc_config_pkg::NumI2c-1:0][3:0] | I2C debug status synchronized bit by bit to clk_smc_i, so bits are not coherent with each other. |
axil_uart_req_smc_clk_i | input | smc_pkg::smc_axil_32_32_req_t | UART register request from the SMC-clock crossbar. |
axil_uart_resp_smc_clk_o | output | smc_pkg::smc_axil_32_32_resp_t | UART register response to the SMC-clock crossbar. |
axil_uart_req_periph_clk_o | output | smc_pkg::smc_axil_32_32_req_t | UART register request to uart_wrap on the peripheral clock. |
axil_uart_resp_periph_clk_i | input | smc_pkg::smc_axil_32_32_resp_t | UART register response from uart_wrap on the peripheral clock. |
axil_log_engine_req_smc_clk_o | output | smc_pkg::smc_axil_56_64_req_t | Log-engine fetch request to the SMC fabric on clk_smc_i. |
axil_log_engine_resp_smc_clk_i | input | smc_pkg::smc_axil_56_64_resp_t | Log-engine fetch response from the SMC fabric on clk_smc_i. |
axil_log_engine_req_periph_clk_i | input | smc_pkg::smc_axil_56_64_req_t | Log-engine fetch request from uart_wrap on the peripheral clock. |
axil_log_engine_resp_periph_clk_o | output | smc_pkg::smc_axil_56_64_resp_t | Log-engine fetch response to uart_wrap on the peripheral clock. |
uart_enable_smc_clk_o | output | logic [smc_config_pkg::NumUart-1:0] | Per-UART enable synchronized to clk_smc_i. |
uart_enable_periph_clk_i | input | logic [smc_config_pkg::NumUart-1:0] | Per-UART enable from uart_wrap on the peripheral clock. |
uart_irq_combined_smc_clk_o | output | logic [smc_config_pkg::NumUart-1:0] | Per-UART OR of the UART interrupt, UART error and log-engine interrupt, flopped on the peripheral clock and synchronized to the SMC clock. |
uart_err_periph_clk_i | input | logic [smc_config_pkg::NumUart-1:0] | UART error indication from each UART, merged into the combined interrupt. |
uart_irq_periph_clk_i | input | logic [smc_config_pkg::NumUart-1:0] | UART interrupt from each UART, merged into the combined interrupt. |
log_engine_irq_periph_clk_i | input | logic [smc_config_pkg::NumUart-1:0] | Log-engine interrupt from each UART, merged into the combined interrupt. |
axil_i3c_req_smc_clk_i | input | smc_pkg::smc_axil_32_32_req_t | I3C register request from the SMC-clock crossbar. |
axil_i3c_resp_smc_clk_o | output | smc_pkg::smc_axil_32_32_resp_t | I3C register response to the SMC-clock crossbar. |
axil_i3c_req_periph_clk_o | output | smc_pkg::smc_axil_32_32_req_t | I3C register request to the I3C controllers on the peripheral clock. |
axil_i3c_resp_periph_clk_i | input | smc_pkg::smc_axil_32_32_resp_t | I3C register response from the I3C controllers on the peripheral clock. |
i3c_irqs_smc_clk_o | output | logic [smc_config_pkg::NumI3c-1:0] | Per-instance I3C interrupt synchronized to clk_smc_i. |
i3c_irqs_periph_clk_i | input | logic [smc_config_pkg::NumI3c-1:0] | Per-instance I3C interrupt on the peripheral clock. |
avsbus_irq_periph_clk_i | input | logic | AVSBus controller interrupt on the peripheral clock. |
avsbus_irq_smc_clk_o | output | logic | AVSBus controller interrupt synchronized to clk_smc_i. |
i2c_cg_en_smc_clk_i | input | logic | I2C clock-gate control on clk_smc_i; high gates the clock off. |
i2c_cg_en_periph_clk_o | output | logic | I2C clock-gate control synchronized to clk_periph_i. |
uart_cg_en_smc_clk_i | input | logic | UART clock-gate control on clk_smc_i; high gates the clock off. |
uart_cg_en_periph_clk_o | output | logic | UART clock-gate control synchronized to clk_periph_i. |
avs_cg_en_smc_clk_i | input | logic | AVSBus clock-gate control on clk_smc_i; high gates the clocks off. |
avs_cg_en_periph_clk_o | output | logic | AVSBus clock-gate control synchronized to clk_periph_i. |
i3c_cg_en_smc_clk_i | input | logic | I3C clock-gate control on clk_smc_i; high gates the clock off. |
i3c_cg_en_periph_clk_o | output | logic | I3C clock-gate control synchronized to clk_periph_i. |
avs_cg_en_ref_clk_o | output | logic | AVSBus clock-gate control synchronized to clk_ref_i. |
tel_cg_en_smc_clk_i | input | logic | Telemetry clock-gate control on clk_smc_i; high gates the clock off. |
tel_cg_en_telemetry_clk_o | output | logic | Telemetry clock-gate control synchronized to clk_telemetry_i. |
ndmreset_request_i | input | logic [smc_config_pkg::CpuClusterCount-1:0] | Asynchronous NDM reset request from each CPU cluster, one bit per cluster. |
ndmreset_request_smc_clk_o | output | logic [smc_config_pkg::CpuClusterCount-1:0] | NDM reset requests after a three-stage synchronizer into clk_smc_i. |
avsbus_cur_state_debug_i | input | logic [16:0] | AVSBus controller state for the debug bus, on the peripheral clock. |
avsbus_cur_state_debug_o | output | logic [16:0] | AVSBus controller state carried to the SMC clock by a handshake data synchronizer. |