smc_reset_ctrl

Derive the SMC primary, warm, and watchdog resets from the pad resets.

Stretches powergood by 32 reference clock cycles, de-glitches the cold reset and the cool-reset pin over 32 reference clock cycles, and extends the cold-reset release by 255 cycles. The primary reset combines the cold, cool-pin and FLR cool resets; the warm reset adds the watchdog and fuse resets. The watchdog reset combines the external and SMC watchdog requests and is held 32 reference clock cycles after both release. The outputs are not synchronized to any destination clock.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_ref_i`	input	`logic`	Reference clock for the powergood stretcher, de-glitchers and cold-reset extender.
`powergood_i`	input	`logic`	Powergood from the pad (BP_POWERGOOD), active-high; low asynchronously clears the stretcher and the de-glitchers.
`rst_cold_ni`	input	`logic`	Cold reset from the pad (BP_RESETN), active-low; must stay low 32 reference clock cycles to take effect.
`fuse_reset_ni`	input	`logic`	Fuse reset, active-low; released once fuse sensing is done and DFT is complete; holds the warm reset.
`rst_ext_wdt_ni`	input	`logic`	External watchdog request, active-low; asserts the watchdog reset.
`smc_wdt_first_timeout_i`	input	`logic`	SMC CPU watchdog first-timeout indication; not used in this module.
`smc_wdt_second_timeout_i`	input	`logic`	SMC watchdog request (CPU watchdog second timeout), active-high; asserts the watchdog reset.
`rst_cool_from_pin_ni`	input	`logic`	Cool reset received by secondary chiplets, active-low; de-glitched over 32 reference clock cycles into the primary reset.
`rst_cool_from_flr_ni`	input	`logic`	FLR cool reset generated by primary chiplets and sent to secondary chiplets, active-low; asserts the primary reset directly.
`powergood_stable_o`	output	`logic`	Powergood that falls with powergood_i and rises 32 reference clock cycles after it.
`stable_cold_rst_no`	output	`logic`	De-glitched cold reset, active-low, released 255 reference clock cycles after the de-glitched input releases; low while powergood_stable_o is low.
`rst_primary_no`	output	`logic`	Primary reset, active-low: the stable cold, de-glitched cool-pin and FLR cool resets combined.
`rst_warm_no`	output	`logic`	Warm reset, active-low: the primary, WDT and fuse resets combined.
`rst_wdt_no`	output	`logic`	Watchdog reset, active-low: either watchdog request, held 32 reference clock cycles after both release.
`test_en_i`	input	`logic`	Scan test mode enable, active-high; selects scan_rst_ni in place of the stretched powergood, the de-glitched cold reset and the stretched watchdog reset.
`scan_rst_ni`	input	`logic`	Scan reset, active-low, used in place of the stretched powergood, the de-glitched cold reset and the stretched watchdog reset while test_en_i is high.