smc_reset_sync
Synchronize SMC resets into the SMC, reference, and peripheral clocks.
Produces async-assert / sync-deassert resets for each SMC clock via prim_sync_reset. Fans synchronized cold, primary, warm, and WDT resets out to the SMC, reference, and peripheral domains.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_smc_i | input | logic | SMC core clock; destination of the cold, primary, warm and WDT synchronizers. |
clk_ref_i | input | logic | Reference clock; destination of the cold and primary synchronizers. |
clk_periph_i | input | logic | Peripheral clock; destination of the primary synchronizer. |
rst_cold_stable_ni | input | logic | De-glitched and extended cold reset from the reset controller, active-low. |
rst_primary_ni | input | logic | Primary reset from the reset controller, active-low and asynchronous. |
rst_warm_ni | input | logic | Warm reset after the JTAG override, active-low and asynchronous. |
rst_wdt_ni | input | logic | Watchdog reset from the reset controller, active-low and asynchronous. |
rst_cold_smc_no | output | logic | Stable cold reset, active-low, with deassertion synchronized to the SMC core clock. |
rst_primary_smc_clk_no | output | logic | Primary reset, active-low, with deassertion synchronized to the SMC core clock. |
rst_warm_smc_clk_no | output | logic | Warm reset, active-low, with deassertion synchronized to the SMC core clock. |
rst_wdt_smc_clk_no | output | logic | Watchdog reset, active-low, with deassertion synchronized to the SMC core clock. |
rst_cold_ref_clk_no | output | logic | Stable cold reset, active-low, with deassertion synchronized to the reference clock. |
rst_primary_ref_clk_no | output | logic | Primary reset, active-low, with deassertion synchronized to the reference clock. |
rst_primary_periph_clk_no | output | logic | Primary reset, active-low, with deassertion synchronized to the peripheral clock. |
test_en_i | input | logic | Scan test mode enable, active-high; selects scan_rst_ni in place of every reset this module generates. |
scan_rst_ni | input | logic | Scan reset, active-low, that replaces the generated resets while test_en_i is high. |