smc_reset_unit
Generate SMC cold, warm, cool, and domain resets.
Combines powergood, the external cold reset, the cool-reset pin, the FLR cool reset, the watchdogs and the fuse reset into primary, warm and watchdog resets synchronized to the SMC, reference and peripheral clocks. Exposes FLR isolation, memory-repair skip, and the cool reset distributed to other chiplets. Drives the per-subsystem reset controls and the sync IRQ from the reset-unit registers. JTAG overrides the fuse, cold, cool, warm and per-subsystem resets; test_en_i substitutes scan_rst_ni for the synchronized resets.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_ref_i | input | logic | Reference clock for the powergood stretcher, reset de-glitchers and FLR counters. |
clk_smc_i | input | logic | SMC core clock for the reset-unit registers and FLR isolation logic. |
clk_periph_i | input | logic | Peripheral clock; only the peripheral-clock primary reset synchronizer uses it. |
powergood_i | input | logic | Power-good from the pad, active-high; holds the cold, primary and warm resets asserted while low, and its release is stretched 32 reference clock cycles to form powergood_stable_o. |
powergood_stable_o | output | logic | Powergood after the stretcher: falls asynchronously with powergood_i and rises 32 reference clock cycles after it. |
rst_cold_ni | input | logic | External cold reset, active-low, before the JTAG override; de-glitched over 32 reference clock cycles and its release extended by 255 cycles. |
fuse_reset_ni | input | logic | Active-low reset that the eFuse controller releases once fuse sensing completes; holds the warm reset asserted, subject to the JTAG override. |
rst_cold_stable_ref_clk_no | output | logic | De-glitched and extended cold reset, active-low, with deassertion synchronized to the reference clock; also resets the FLR counters. |
rst_cold_stable_smc_clk_no | output | logic | De-glitched and extended cold reset, active-low, with deassertion synchronized to the SMC core clock; also resets the FLR isolation registers. |
jtag_reset_ctrl_i | input | smc_pkg::jtag_smc_reset_ctrl_t | JTAG reset overrides in the TCK domain: an override select and value for the fuse, cold, cool, and warm resets and for each subsystem's cold and warm reset. |
reg_axi_lite_req_i | input | smc_pkg::smc_axil_32_32_req_t | AXI-Lite Register Interface request. |
reg_axi_lite_resp_o | output | smc_pkg::smc_axil_32_32_resp_t | AXI-Lite Register Interface response. |
rst_ext_wdt_ni | input | logic | External watchdog reset, active-low and asynchronous; asserts the WDT reset and, through it, the warm reset. |
smc_wdt_first_timeout_i | input | logic | SMC CPU watchdog first-timeout indication, the OR of the per-core watchdog timeouts; not used by the reset logic. |
smc_wdt_second_timeout_i | input | logic | SMC CPU watchdog second-timeout indication, active-high; asserts the WDT reset and, through it, the warm reset. |
isolate_req_pin_i | input | logic | Isolation request from the external pin, active-high, synchronized to the SMC core clock; raises the isolate_req_o bits enabled in ISOLATE_REQ_PINEN_REG and skip_mem_repair_o. |
cfg_flr_pf_active_i | input | logic | PCIe function-level reset request, active-high; its rising edge sets ISOLATE_REQ_SMC and starts the FLR cool-reset counters. |
rst_cool_ni | input | logic | Cool reset from the pin, active-low; de-glitched over 32 reference clock cycles into the primary reset, and visible in ISOLATE_REQ_VIS. |
isolate_req_o | output | logic [31:0] | Per-subsystem isolation requests on the SMC core clock: ISOLATE_REQ_REG, OR the pin-enabled bits while the pin is high, OR the SMCEN-enabled bits while ISOLATE_REQ_SMC is set. |
skip_mem_repair_o | output | logic | High while the isolate pin or ISOLATE_REQ_SMC is set, to skip memory repair and MBIST during FLR. |
rst_cool_no | output | logic | FLR cool reset after the JTAG override, active-low, on the reference clock; also asserts the primary reset and is sent to other chiplets. |
ss_reset_complete_i | input | logic [31:0] | Reset-complete indication from each subsystem, one bit per subsystem; synchronized to the SMC core clock and reported in the SS_RESET_COMPLETE register. |
ss_config_o | output | logic [31:0] | Per-subsystem configuration bits from the SS_CONFIG register, lockable per bit through SS_CONFIG_LOCK; cleared by the primary reset. |
ss_reset_ctrl_o | output | smc_reset_unit_pkg::reset_ctrl_t | Per-subsystem reset controls from the reset-unit registers: cold and warm resets after the JTAG override, the hold qualifiers, and force-to-reference-clock. The resets leave unsynchronized; each subsystem synchronizes them. |
rst_primary_ref_clk_no | output | logic | Primary reset, active-low, with deassertion synchronized to the reference clock. |
rst_primary_smc_clk_no | output | logic | Primary reset, active-low, with deassertion synchronized to the SMC core clock. |
rst_warm_smc_clk_no | output | logic | Warm reset, active-low, with deassertion synchronized to the SMC core clock; also asserted by the primary, watchdog, and fuse resets. |
rst_wdt_smc_clk_no | output | logic | Watchdog reset, active-low, asserted by the external watchdog reset or the SMC watchdog second timeout; deassertion synchronized to the SMC core clock. |
rst_primary_periph_clk_no | output | logic | Primary reset, active-low, with deassertion synchronized to the peripheral clock. |
sync_irq_o | output | logic | Global sync bit, driven directly by the SYNC_REG register. |
test_en_i | input | logic | Scan test mode enable, active-high; selects scan_rst_ni in place of the stretched powergood and the synchronized cold, primary, warm and WDT resets. |
scan_rst_ni | input | logic | Scan reset, active-low, that replaces the stretched powergood and the synchronized resets while test_en_i is high. |