smc_subsystem_resets

Fan SMC reset-unit controls out to per-subsystem resets.

Drives one reset_ctrl_t per subsystem, 32 in all, from the SS_* reset-unit registers. Implements the external SS_CONFIG and SS_COLD_RESET_N registers with per-bit write locks and reports the synchronized SS_RESET_COMPLETE inputs.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	SMC core clock.
`rst_primary_ni`	input	`logic`	Primary reset, active-low, synchronized to clk_i: the stable cold, cool-pin and FLR cool resets combined. Clears SS_CONFIG and SS_COLD_RESET_N, which holds every subsystem cold reset asserted.
`hwif_out_i`	input	`reset_unit_reg_pkg::reset_unit__out_t`	Reset-unit register outputs: the SS_* register values and the SS_CONFIG and SS_COLD_RESET_N access strobes.
`hwif_in_o`	output	`reset_unit_reg_pkg::reset_unit__in_t`	Reset-unit register inputs for SS_RESET_COMPLETE, SS_CONFIG and SS_COLD_RESET_N; every other field is zero.
`ss_reset_complete_i`	input	`logic [31:0]`	Reset-complete indication from each subsystem, one bit per subsystem; synchronized to clk_i and reported in the SS_RESET_COMPLETE register.
`ss_config_o`	output	`logic [31:0]`	Per-subsystem configuration bits from the SS_CONFIG register, lockable per bit through SS_CONFIG_LOCK; cleared by the primary reset.
`ss_reset_ctrl_o`	output	`smc_reset_unit_pkg::reset_ctrl_t`	Per-subsystem reset controls from the SS_COLD_RESET_N, SS_WARM_RESET_N, hold, and SS_FORCE_TO_REF_CLK registers; SS_COLD_RESET_N bits are write-locked by SS_COLD_RESET_LOCK.