tilelink_to_rom_mem

Bridge TileLink Gets to the SMC boot ROM memory interface.

Converts TileLink Get traffic into a ROM address and chip-enable; every A-channel request is answered as a read, since the port carries no opcode. Optionally swaps response endianness before returning data on the D channel.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ADDR_WIDTH`	`int unsigned`	`14`	Width of the ROM word address, taken from the TileLink byte address starting at bit 3.
`WORD_WIDTH`	`int unsigned`	`64`	Width of a ROM word and of the D-channel data; the endianness swap assumes 64.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Clock of the cluster boot ROM TileLink port.
`rst_i`	input	`logic`	Active-high asynchronous reset from the cluster boot ROM TileLink port.
`auto_in_a_ready`	output	`logic`	A-channel ready; follows auto_in_d_ready.
`auto_in_a_valid`	input	`logic`	A-channel Get request valid.
`auto_in_a_bits_size`	input	`logic [1:0]`	A-channel transfer size, returned on auto_in_d_bits_size.
`auto_in_a_bits_source`	input	`logic [14:0]`	A-channel source ID, returned on auto_in_d_bits_source.
`auto_in_a_bits_address`	input	`logic [31:0]`	A-channel byte address; bits 3 and up select the ROM word.
`auto_in_d_ready`	input	`logic`	D-channel ready from the cluster; also used as the A-channel ready.
`auto_in_d_valid`	output	`logic`	D-channel response valid, set the cycle after a request is accepted and cleared by auto_in_d_ready.
`auto_in_d_bits_size`	output	`logic [1:0]`	Transfer size of the request being answered.
`auto_in_d_bits_source`	output	`logic [14:0]`	Source ID of the request being answered.
`auto_in_d_bits_data`	output	`logic [WORD_WIDTH-1:0]`	ROM word returned on the D channel, byte-reversed when rom_flip_endianness_i is high.
`rom_flip_endianness_i`	input	`logic`	High byte-reverses rom_bank_data_i before it is returned on the D channel.
`rom_address_o`	output	`logic [ADDR_WIDTH-1:0]`	ROM word address: the incoming address while a request is accepted, otherwise the last accepted one.
`mem_chip_en_o`	output	`logic`	ROM chip enable, high while an A-channel request or D-channel response is valid; low in reset.
`rom_bank_data_i`	input	`logic [63:0]`	ROM word read at rom_address_o, passed combinationally to auto_in_d_bits_data.