smu

Integrate SMC, optional SEP, DTP, and SMU fabric services.

Bring up clocks and cold reset, host the primary JTAG/DTP path, route the SMU AXI crossbar toward SMN, and expose SMC and SEP memory, eFuse, GPIO, telemetry, reset-unit, and debug interfaces to the integrator. When CFG.SEP is 0, SEP apertures and SEP-gated ports are tied off, and the SMC connects to the external AXI ports through ID-width converters instead of the crossbar.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CFG_IDX`	`int unsigned`	`0`	Selects the smu_pkg::SmuConfigs preset that CFG defaults to, 0 for DefaultCfg and 1 for NoSepCfg; a CFG set directly takes precedence. The type is int unsigned so that SpyGlass elaborate -param can override it; -param cannot set a struct.
`CFG`	`smu_pkg::smu_cfg_t`	`smu_pkg::SmuConfigs[CFG_IDX]`	SMU configuration; set directly, it takes precedence over CFG_IDX. The smu_cfg_t field clauses give each field's meaning and limits.
`NumCpuCores`	`int unsigned`	`smc_4core_cpu_pkg::NumCpuCores`	SMC CPU core count.
`NumCpuInterrupts`	`int unsigned`	`smc_4core_cpu_pkg::NumCpuInterrupts`	Per-core CPU interrupt count.
`NumExtInterrupts`	`int unsigned`	`smc_4core_cpu_pkg::NumExtInterrupts`	External interrupt count into the SMC.
`NumSramBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumSramBanks`	SMC scratch-RAM bank count.
`NumIcacheTagBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumIcacheTagBanks`	SMC L1 I-cache tag bank count.
`NumIcacheDataBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumIcacheDataBanks`	SMC L1 I-cache data bank count.
`NumDcacheTagBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumDcacheTagBanks`	SMC L1 D-cache tag bank count.
`NumDcacheDataBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumDcacheDataBanks`	SMC L1 D-cache data bank count.
`XtrigNumCtp`	`int unsigned`	`CFG.XTRIG_NUM_CTP`	External cross-trigger port count from CFG, forwarded to the DTP XTRIG_NUM_CTP.
`XtrigNumIntCt`	`int unsigned`	`CFG.XTRIG_NUM_INT_CT`	SMU-exposed internal CT lane count from CFG.
`XtrigNumClkStopReq`	`int unsigned`	`CFG.XTRIG_NUM_CLK_STOP_REQ`	SMU-exposed clock-stop request count from CFG.
`DtpXtrigNumIntCt`	`int unsigned`	`smu_pkg::dtp_xtrig_num_int_ct(CFG)`	Internal CT count including SMC-reserved lanes, forwarded to the DTP XTRIG_NUM_INT_CT.
`DtpXtrigNumClkStopReq`	`int unsigned`	`smu_pkg::dtp_xtrig_num_clk_stop_req(CFG)`	Clock-stop count including SMC-reserved lanes, forwarded to the DTP XTRIG_NUM_CLK_STOP_REQ.
`JtagNumExtraStapPorts`	`int unsigned`	`smu_pkg::jtag_num_extra_stap_ports(CFG)`	Extra STAP port count; at least one for tie-off.
`DtpXtrigIntCtMode`	`smu_pkg::dtp_ct_mode_t`	`smu_pkg::dtp_xtrig_int_ct_mode(CFG)`	Per-lane CTM mode vector with SMC lanes forced to 0; its low DtpXtrigNumIntCt bits are forwarded to the DTP XTRIG_INT_CT_MODE.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_smu_i`	input	`logic`	SMU clock; clocks the SMC core, the SEP, the DTP and the SMU AXI crossbar.
`clk_ref_i`	input	`logic`	Reference clock for cold-reset and always-on logic; forwarded to the SMC and the SEP.
`clk_periph_i`	input	`logic`	Peripheral clock, forwarded to the SMC.
`rst_cold_ni`	input	`logic`	Cold reset, active-low; the SMC de-glitches and extends it.
`rst_cold_stable_ref_clk_no`	output	`logic`	De-glitched and extended cold reset, active-low, synchronized to clk_ref_i.
`powergood_i`	input	`logic`	Chip power-good from the pad, active-high. While low it asynchronously resets the SMC powergood stretcher and cold-reset de-glitcher; the stretched copy is the DTP and SEP debug power-on reset.
`jtag_ptap_client_tap_ctrl_i`	input	`prim_jtag_pkg::jtag_tap_ctrl_t`	Primary TAP control from the pad.
`jtag_ptap_client_tdi_i`	input	`logic`	Primary TAP TDI.
`jtag_ptap_client_tdo_o`	output	`logic`	Primary TAP TDO.
`jtag_ptap_client_tdo_oen_o`	output	`logic`	Primary TAP TDO output enable.
`jtag_bsr_host_scan_ctrl_o`	output	`prim_jtag_pkg::jtag_scan_ctrl_t`	Boundary-scan host scan control.
`jtag_bsr_host_scan_in_i`	input	`logic`	Boundary-scan chain input.
`jtag_bsr_host_scan_out_o`	output	`logic`	Boundary-scan chain output.
`jtag_stap_io_host_tap_ctrl_o`	output	`prim_jtag_pkg::jtag_tap_ctrl_t`	I/O STAP host TAP control.
`jtag_stap_io_host_tdi_i`	input	`logic`	I/O STAP TDI.
`jtag_stap_io_host_tdo_o`	output	`logic`	I/O STAP TDO.
`jtag_stap_io_host_tdo_oen_o`	output	`logic`	I/O STAP TDO output enable.
`jtag_stap_extra_host_tap_ctrl_o`	output	`prim_jtag_pkg::jtag_tap_ctrl_t`	Extra STAP host TAP controls.
`jtag_stap_extra_host_tdi_i`	input	`logic`	Extra STAP TDI bits.
`jtag_stap_extra_host_tdo_o`	output	`logic`	Extra STAP TDO bits.
`jtag_stap_extra_host_tdo_oen_o`	output	`logic`	Extra STAP TDO output enables.
`jtag_stap_host_scan_ctrl_o`	output	`prim_jtag_pkg::jtag_scan_ctrl_t`	Extended STAP scan control.
`jtag_stap_host_scan_in_i`	input	`logic`	Extended STAP scan input.
`jtag_stap_host_scan_out_o`	output	`logic`	Extended STAP scan output.
`jtag_dfd_host_scan_ctrl_o`	output	`prim_jtag_pkg::jtag_scan_ctrl_t`	DFD iJTAG scan control.
`jtag_dfd_host_scan_in_i`	input	`logic`	DFD iJTAG scan input.
`jtag_dfd_host_scan_out_o`	output	`logic`	DFD iJTAG scan output.
`jtag_dft_secure_host_scan_ctrl_o`	output	`prim_jtag_pkg::jtag_scan_ctrl_t`	Secure DFT iJTAG scan control.
`jtag_dft_secure_host_scan_in_i`	input	`logic`	Secure DFT iJTAG scan input.
`jtag_dft_secure_host_scan_out_o`	output	`logic`	Secure DFT iJTAG scan output.
`jtag_dft_host_scan_ctrl_o`	output	`prim_jtag_pkg::jtag_scan_ctrl_t`	Non-secure DFT iJTAG scan control.
`jtag_dft_host_scan_in_i`	input	`logic`	Non-secure DFT iJTAG scan input.
`jtag_dft_host_scan_out_o`	output	`logic`	Non-secure DFT iJTAG scan output.
`dtp_stop_clks_o`	output	`logic`	Registered OR of the DTP DEBUG_CONTROL clock stop and the DTP clock-stop request lanes, including the SMC CLA lane.
`jtag_ptap_state_o`	output	`jtag_tap_pkg::tap_state_e`	Primary TAP FSM state.
`jtag_ptap_inst_decoded_o`	output	`jtag_inst_reg_pkg::jtag_instruction_decoded_e`	Decoded primary TAP instruction.
`jtag_ic_reset_ext_o`	output	`ic_reset_ext_t`	External IC_RESET TDR slice toward the integrator, a typed packed struct with .ovrd and .val halves.
`xtrig_ctm_src_req_o`	output	`logic [XtrigNumIntCt-1:0]`	CTM source requests toward sinks; the SMC-reserved lanes stay inside the SMU.
`xtrig_ctm_src_ack_i`	input	`logic [XtrigNumIntCt-1:0]`	CTM source acknowledges from sinks.
`xtrig_ctm_dst_req_i`	input	`logic [XtrigNumIntCt-1:0]`	CTM destination requests from sources.
`xtrig_ctm_dst_ack_o`	output	`logic [XtrigNumIntCt-1:0]`	CTM destination acknowledges toward sources.
`xtrig_clk_stop_req_i`	input	`logic [XtrigNumClkStopReq-1:0]`	Per-lane clock-stop requests into the CTN; the SMC-reserved lane stays inside the SMU.
`xtrig_ctp_req_out_dout_o`	output	`logic [XtrigNumCtp-1:0]`	CTP req-out pad data.
`xtrig_ctp_req_out_dout_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP req-out pad output enable.
`xtrig_ctp_req_out_din_i`	input	`logic [XtrigNumCtp-1:0]`	CTP req-out pad input.
`xtrig_ctp_req_out_din_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP req-out pad input enable.
`xtrig_ctp_req_in_dout_o`	output	`logic [XtrigNumCtp-1:0]`	CTP req-in pad data.
`xtrig_ctp_req_in_dout_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP req-in pad output enable.
`xtrig_ctp_req_in_din_i`	input	`logic [XtrigNumCtp-1:0]`	CTP req-in pad input.
`xtrig_ctp_req_in_din_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP req-in pad input enable.
`xtrig_ctp_ack_in_dout_o`	output	`logic [XtrigNumCtp-1:0]`	CTP ack-in pad data.
`xtrig_ctp_ack_in_dout_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP ack-in pad output enable.
`xtrig_ctp_ack_in_din_i`	input	`logic [XtrigNumCtp-1:0]`	CTP ack-in pad input.
`xtrig_ctp_ack_in_din_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP ack-in pad input enable.
`xtrig_ctp_ack_out_dout_o`	output	`logic [XtrigNumCtp-1:0]`	CTP ack-out pad data.
`xtrig_ctp_ack_out_dout_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP ack-out pad output enable.
`xtrig_ctp_ack_out_din_i`	input	`logic [XtrigNumCtp-1:0]`	CTP ack-out pad input.
`xtrig_ctp_ack_out_din_en_o`	output	`logic [XtrigNumCtp-1:0]`	CTP ack-out pad input enable.
`rst_primary_ref_clk_no`	output	`logic`	Primary reset, active-low, synchronized to clk_ref_i.
`rst_primary_smc_clk_no`	output	`logic`	Primary reset, active-low, synchronized to clk_smu_i; it also resets the DTP, the SEP and the SMU AXI crossbar.
`rst_primary_periph_clk_no`	output	`logic`	Primary reset, active-low, synchronized to clk_periph_i.
`smu_axi_in_req_i`	input	`smu_axi_xbar_pkg::axi_56_64_req_t`	External AXI request into the SMU. The crossbar routes it to the SEP or SMC aperture and returns a decode error for any other address; when CFG.SEP is 0 it goes to the SMC through an ID-width converter.
`smu_axi_in_resp_o`	output	`smu_axi_xbar_pkg::axi_56_64_resp_t`	External AXI response from the SMU.
`smu_axi_out_req_o`	output	`smu_axi_xbar_pkg::axi_out_req_t`	Outbound AXI request toward the external system, carrying SEP and SMC requests that match neither aperture; when CFG.SEP is 0 it carries every SMC outbound request.
`smu_axi_out_resp_i`	input	`smu_axi_xbar_pkg::axi_out_resp_t`	External system response to smu_axi_out_req_o.
`smc_external_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	SMC AXI-Lite request toward adopter peripherals.
`smc_external_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	Adopter peripheral AXI-Lite response.
`smc_efuse_bank_ctrl_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	SMC eFuse bank-control AXI-Lite request.
`smc_efuse_bank_ctrl_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	SMC eFuse bank-control AXI-Lite response.
`smc_efuse_shim_command_req_o`	output	`smc_efuse_pkg::fuse_command_req_t`	SMC eFuse shim command request.
`smc_efuse_shim_command_resp_i`	input	`smc_efuse_pkg::fuse_command_resp_t`	SMC eFuse shim command response.
`smc_shadow_regs_o`	output	`smc_efuse_pkg::efuse_map_t`	SMC eFuse shadow-register map.
`lsio_interface_select_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Per-GPIO-wrap LSIO interface select.
`pad2core_i`	input	`logic [smc_pkg::NumGpioWraps-1:0]`	GPIO pad-to-core data.
`core2pad_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	GPIO core-to-pad data.
`pad2core_en_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	GPIO pad-to-core input enables.
`core2pad_en_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	GPIO core-to-pad output enables.
`rst_cool_n_from_pin_i`	input	`logic`	Cool reset from the package pin, active-low.
`clk_telemetry_i`	input	`logic`	ATB telemetry clock.
`rst_telemetry_ni`	input	`logic`	ATB telemetry reset, active-low.
`telemetry_atdata_i`	input	`telemetry_receiver_pkg::telemetry_data_t [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB telemetry data from receivers.
`telemetry_atid_i`	input	`telemetry_receiver_pkg::atb_id_t [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB telemetry IDs from receivers.
`telemetry_atready_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB ready toward telemetry sources.
`telemetry_atvalid_i`	input	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB valid from telemetry sources.
`telemetry_afvalid_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB flush valid toward telemetry sources.
`telemetry_afready_i`	input	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB flush ready from telemetry sources.
`smc_cluster_ded_o`	output	`logic`	SMC CPU cluster uncorrectable (double-error-detected) memory error.
`smc_wdt_first_timeout_o`	output	`logic`	SMC first-stage watchdog timeout, the OR of the per-core CPU watchdog timeouts.
`smc_wdt_second_timeout_o`	output	`logic`	SMC second-stage watchdog timeout, which also asserts the SMC watchdog reset.
`smc_global_base_o`	output	`smc_pkg::smc_axi_addr_t`	SMC aperture base from the SMC GLOBAL_BASE register for external decoders and NoC routing; it also sets the SMC aperture of the SMU crossbar.
`smc_region_size_o`	output	`logic [31:0]`	SMC aperture size in bytes from the SMC REGION_SIZE register; it also sets the SMC aperture of the SMU crossbar.
`sep_global_base_o`	output	`logic [sep_pkg::SEP_SYSTEM_PERIPHERALS_56_ADDR_WIDTH-1:0]`	SEP aperture base from the SEP_GLOBAL_BASE_ADDR register for external decoders; it also sets the SEP aperture of the SMU crossbar. Tied to 0 when CFG.SEP is 0.
`sep_region_size_o`	output	`logic [sep_pkg::SEP_SYSTEM_PERIPHERALS_56_ADDR_WIDTH-1:0]`	SEP aperture size in bytes from the zero-extended SEP_REGION_SIZE register; the SMU crossbar uses its low 32 bits. Tied to 0 when CFG.SEP is 0.
`smc_ext_interrupts_i`	input	`logic [CFG.NUM_INT_TO_SMC-1:0]`	External interrupts into the SMC, zero-extended to the SMC's NumExtInterrupts inputs.
`smc_fuse_sense_done_o`	output	`logic`	SMC fuse sense complete.
`smc_fuse_reset_n_delayed_o`	output	`logic`	Fuse-released SMC reset, active-low, delayed by 16 SMC clock stages and held low while boot stall is asserted.
`skip_mem_repair_o`	output	`logic`	Skip memory repair during boot.
`ext_boot_seq_done_i`	input	`logic`	External boot sequence complete.
`lc_state_o`	output	`logic [2*smc_pkg::LcStateWidth-1:0]`	Lifecycle state driven by the SEP; fixed at 8'hF0 when CFG.SEP is 0.
`lc_sigint_err_o`	output	`logic`	Lifecycle signal-integrity error, the OR of the SEP and SMC eFuse differential-encoding errors.
`smc_ndmreset_request_i`	input	`logic [smc_config_pkg::CpuClusterCount - 1:0]`	Per-cluster NDM reset requests.
`smc_ndmreset_process_o`	output	`logic [smc_config_pkg::CpuClusterCount - 1:0]`	Per-cluster NDM reset in-progress.
`smc_ext_mailbox_interrupts_o`	output	`logic [smc_pkg::NumMailboxes-1:0]`	Mailbox interrupts toward the SMC.
`cfg_flr_pf_active_i`	input	`logic`	Function-level reset / PF-active configuration.
`isolate_req_o`	output	`logic [31:0]`	Per-subsystem isolate requests.
`ss_reset_complete_i`	input	`logic [31:0]`	Per-subsystem reset-complete status.
`ss_config_o`	output	`logic [31:0]`	Per-subsystem reset-unit configuration.
`ss_reset_ctrl_o`	output	`smc_reset_unit_pkg::reset_ctrl_t`	Per-subsystem reset control structs.
`sync_irq_o`	output	`logic`	Synchronized reset-unit interrupt.
`smc_rom_intf_req_o`	output	`smc_rom_req_t`	SMC ROM hard-macro request.
`smc_rom_intf_rsp_i`	input	`smc_rom_rsp_t`	SMC ROM hard-macro response.
`smc_scratch_ram_intf_req_o`	output	`smc_scratch_ram_req_t`	SMC scratch-RAM bank requests.
`smc_scratch_ram_intf_rsp_i`	input	`smc_scratch_ram_rsp_t`	SMC scratch-RAM bank responses.
`smc_l1_icache_tag_intf_req_o`	output	`smc_l1_icache_tag_req_t`	SMC L1 I-cache tag bank requests.
`smc_l1_icache_tag_intf_rsp_i`	input	`smc_l1_icache_tag_rsp_t`	SMC L1 I-cache tag bank responses.
`smc_l1_icache_data_intf_req_o`	output	`smc_l1_icache_data_req_t`	SMC L1 I-cache data bank requests.
`smc_l1_icache_data_intf_rsp_i`	input	`smc_l1_icache_data_rsp_t`	SMC L1 I-cache data bank responses.
`smc_l1_dcache_tag_intf_req_o`	output	`smc_l1_dcache_tag_req_t`	SMC L1 D-cache tag bank requests.
`smc_l1_dcache_tag_intf_rsp_i`	input	`smc_l1_dcache_tag_rsp_t`	SMC L1 D-cache tag bank responses.
`smc_l1_dcache_data_intf_req_o`	output	`smc_l1_dcache_data_req_t`	SMC L1 D-cache data bank requests.
`smc_l1_dcache_data_intf_rsp_i`	input	`smc_l1_dcache_data_rsp_t`	SMC L1 D-cache data bank responses.
`smc_disable_sram_auto_init_i`	input	`logic`	Disable SMC SRAM automatic initialization.
`smc_init_mem_done_o`	output	`logic`	SMC memory initialization complete.
`chiplet_is_primary_i`	input	`logic`	Chiplet is the OCTS primary for the system timer.
`timer_count_o`	output	`logic [63:0]`	System timer count toward OCTS consumers.
`trace_mem_req_o`	output	`trace_mem_pkg::SinkMemPktIn_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Trace-memory sink requests.
`trace_mem_resp_i`	input	`trace_mem_pkg::SinkMemPktOut_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Trace-memory sink responses.
`test_en_i`	input	`logic`	Scan test mode enable, active-high; forwarded to the DTP, the SMC, the SEP and the SMU AXI crossbar.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low; the SMC and the SEP use it in place of functional resets while test_en_i is high. The DTP does not use it.
`mem_repair_done_i`	input	`logic`	Memory repair sequence done.
`mem_repair_success_i`	input	`logic`	Memory repair sequence succeeded.
`mem_repair_abort_i`	input	`logic`	Memory repair sequence aborted.
`mbist_done_i`	input	`logic`	MBIST sequence done.
`mbist_pass_i`	input	`logic`	MBIST sequence passed.
`mbist_abort_i`	input	`logic`	MBIST sequence aborted.
`sep_sram_req_o`	output	`sep_pkg::sep_sram_req_t`	SEP SRAM request toward sep_ip_integration.
`sep_sram_rsp_i`	input	`sep_pkg::sep_sram_rsp_t`	SEP SRAM response from sep_ip_integration.
`sep_boot_rom_req_o`	output	`sep_pkg::sep_sram_req_t`	SEP boot-ROM request toward sep_ip_integration.
`sep_boot_rom_rsp_i`	input	`sep_pkg::sep_sram_rsp_t`	SEP boot-ROM response from sep_ip_integration.
`sep_cpu_tcm_req_o`	output	`sep_pkg::sep_cpu_tcm_req_t`	SEP CPU TCM request toward sep_ip_integration.
`sep_cpu_tcm_rsp_i`	input	`sep_pkg::sep_cpu_tcm_rsp_t`	SEP CPU TCM response from sep_ip_integration.
`sep_efuse_bank_ctrl_req_o`	output	`sep_efuse_pkg::efuse_axil_req_t`	SEP eFuse bank-control AXI-Lite request.
`sep_efuse_bank_ctrl_resp_i`	input	`sep_efuse_pkg::efuse_axil_resp_t`	SEP eFuse bank-control AXI-Lite response.
`sep_efuse_shim_command_req_o`	output	`sep_efuse_pkg::fuse_command_req_t`	SEP eFuse shim command request.
`sep_efuse_shim_command_resp_i`	input	`sep_efuse_pkg::fuse_command_resp_t`	SEP eFuse shim command response.
`sep_crypto_pka_imem_sram_req_o`	output	`sep_crypto_pkg::sep_crypto_pka_imem_sram_req_t`	SEP crypto PKA instruction-memory SRAM request.
`sep_crypto_pka_imem_sram_rsp_i`	input	`sep_crypto_pkg::sep_crypto_pka_imem_sram_rsp_t`	SEP crypto PKA instruction-memory SRAM response.
`sep_crypto_pka_dmem_sram_req_o`	output	`sep_crypto_pkg::sep_crypto_pka_dmem_sram_req_t`	SEP crypto PKA data-memory SRAM request.
`sep_crypto_pka_dmem_sram_rsp_i`	input	`sep_crypto_pkg::sep_crypto_pka_dmem_sram_rsp_t`	SEP crypto PKA data-memory SRAM response.
`abr_mem_req_o`	output	`sep_crypto_pkg::abr_mem_req_t`	Adams Bridge external SRAM request; the technology macros live in sep_ip_integration.
`abr_mem_rsp_i`	input	`sep_crypto_pkg::abr_mem_rsp_t`	Adams Bridge external SRAM response.
`ext_trng_axil_req_o`	output	`sep_pkg::sep_32_32_axil_req_t`	External TRNG AXI-Lite request.
`ext_trng_axil_resp_i`	input	`sep_pkg::sep_32_32_axil_resp_t`	External TRNG AXI-Lite response.
`ext_trng_axis_req_i`	input	`sep_crypto_pkg::ext_trng_axis_req_t`	External TRNG AXI-stream requests.
`ext_trng_axis_rsp_o`	output	`sep_crypto_pkg::ext_trng_axis_rsp_t`	External TRNG AXI-stream responses.
`ext_trng_irq_i`	input	`logic`	External TRNG interrupt.
`entropy_rosc_sample_clk_i`	input	`logic`	Ring-oscillator sample clock for the SEP entropy source, asynchronous to clk_smu_i.
`sep_km_rom_mem_req_o`	output	`km_intf_pkg::km_rom_mem_req_t`	SEP Key Manager ROM memory request.
`sep_km_rom_mem_rsp_i`	input	`km_intf_pkg::km_rom_mem_rsp_t`	SEP Key Manager ROM memory response.
`sep_km_sram_mem_req_o`	output	`km_intf_pkg::km_sram_mem_req_t`	SEP Key Manager SRAM memory request.
`sep_km_sram_mem_rsp_i`	input	`km_intf_pkg::km_sram_mem_rsp_t`	SEP Key Manager SRAM memory response.
`sep_external_req_o`	output	`sep_pkg::sep_32_64_6_12_axi_req_t`	SEP external AXI request.
`sep_external_resp_i`	input	`sep_pkg::sep_32_64_6_12_axi_resp_t`	SEP external AXI response.
`sep_cpu_trace_o`	output	`sep_pkg::sep_cpu_trace_t`	SEP CPU trace bundle.
`sep_lockstep_ctrl_i`	input	`sep_pkg::sep_lockstep_ctrl_t`	SEP lockstep control.
`sep_lockstep_status_o`	output	`sep_pkg::sep_lockstep_status_t`	SEP CPU lockstep corruption-detected status; zero when CFG.SEP is 0 or the core is built without lockstep.
`sep_ext_interrupts_i`	input	`logic [sep_pkg::NUM_EXTERNAL_IRQS-1:0]`	External interrupts into the SEP.
`lcc_demote_state_1_o`	output	`logic [1:0]`	Lifecycle demote state 1.
`lcc_demote_state_2_o`	output	`logic [1:0]`	Lifecycle demote state 2.
`secure_tm_o`	output	`logic`	Secure test-mode indication from the SEP; low when CFG.SEP is 0.
`sep_fuse_dft_disable_o`	output	`logic`	Gate for DFT-inserted SEP OTP access paths, active-high and held high when CFG.SEP is 0. Unconnected in the functional design; DFT insertion connects it.
`smc_fuse_dft_disable_o`	output	`logic`	Gate for DFT-inserted SMC OTP access paths, active-high and held high when CFG.SEP is 0. Unconnected in the functional design; DFT insertion connects it.
`sep_fuse_sense_done_o`	output	`logic`	SEP fuse sense complete.
`clk_sep_wdt_i`	input	`logic`	SEP watchdog timer clock.
`secure_tm_req_i`	input	`logic`	SEP secure test-mode request strap.
`i3c_dat_mem_src_i`	input	`i3c_pkg::dat_mem_src_t [smc_config_pkg::NumI3c-1:0]`	I3C DAT memory source interfaces.
`i3c_dat_mem_sink_o`	output	`i3c_pkg::dat_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	I3C DAT memory sink interfaces.
`i3c_dct_mem_src_i`	input	`i3c_pkg::dct_mem_src_t [smc_config_pkg::NumI3c-1:0]`	I3C DCT memory source interfaces.
`i3c_dct_mem_sink_o`	output	`i3c_pkg::dct_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	I3C DCT memory sink interfaces.
`i3c_rlt_mem_src_i`	input	`i3c_pkg::rlt_mem_src_t [smc_config_pkg::NumI3c-1:0]`	I3C RLT memory source interfaces.
`i3c_rlt_mem_sink_o`	output	`i3c_pkg::rlt_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	I3C RLT memory sink interfaces.
`gated_clk_periph_i3c_o`	output	`logic`	Gated peripheral clock for I3C.
`ext_debug_bus_i`	input	`logic [127:0]`	External debug bus; the SMC receives it above the 384-bit SEP debug bus, which is zero when CFG.SEP is 0. Signals must be 16-bit aligned within it.
`gpio_interrupt_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	GPIO wrap interrupt outputs.
`uart_interrupt_o`	output	`logic [smc_config_pkg::NumUart-1:0]`	UART interrupt outputs.