smu_pkg

Hold System Management Unit configuration types and defaults.

Define smu_cfg_t, the configuration smu takes as CFG, its presets, and the functions that derive the DTP cross-trigger and extra-STAP parameters from it. SmuConfigs lists DefaultCfg at index 0 and NoSepCfg at index 1. CFG defaults to SmuConfigs[CFG_IDX], and a CFG set directly takes precedence over CFG_IDX. NoSepCfg differs from DefaultCfg only in SEP. The JTAG, cross-trigger and pipeline fields configure the DTP instance in smu, each forwarded to the DTP parameter of the same name unless its clause says otherwise. XTRIG_NUM_INT_CT and XTRIG_NUM_CLK_STOP_REQ are the SMU-exposed counts; smu adds the SMC-reserved lanes (XtrigSmcIntCtLanes, XtrigSmcClkStopLanes) before passing them to DTP.

DefaultCfg enables every JTAG feature with one extra STAP and zero ID fields, and sets 16 CTPs, 8 exposed internal CT lanes, 8 exposed clock-stop requests, all lanes in pulse-sync mode, pipeline depths of 3, 256 SMC interrupts, two outstanding SMC AXI-Lite transactions and 4-byte eFuse shim windows. It includes the SEP with a zero secure-disable token, three external TRNG streams, Adams Bridge masking on and a one-cycle Adams Bridge SRAM latency.

`smu_cfg_t`

Packed struct

Table 1. `smu_cfg_t`
Field	Type	Description
`NUM_INT_TO_SMC`	`int unsigned`	Width of smc_ext_interrupts_i, 1 to 256; smu zero-extends it to the 256 SMC external interrupt inputs.
`JTAG_BSR_ENABLE`	`bit`	Enables the mandatory boundary-scan instructions.
`JTAG_EXTEST_TRAIN_ENABLE`	`bit`	Enables the optional EXTEST_TRAIN instruction; needs JTAG_BSR_ENABLE.
`JTAG_EXTEST_PULSE_ENABLE`	`bit`	Enables the optional EXTEST_PULSE instruction; needs JTAG_BSR_ENABLE.
`JTAG_INTEST_ENABLE`	`bit`	Enables the optional INTEST instruction; needs JTAG_BSR_ENABLE.
`JTAG_CLAMP_ENABLE`	`bit`	Reports CLAMP support in JTAG_CAPS; it sets only the CAPS bit, and CLAMP decodes either way.
`JTAG_HIGHZ_ENABLE`	`bit`	Reports HIGHZ support in JTAG_CAPS; it sets only the CAPS bit, and HIGHZ decodes either way.
`JTAG_RUNBIST_ENABLE`	`bit`	Enables the optional RUNBIST instruction.
`JTAG_TMP_ENABLE`	`bit`	Enables the TMP controller and its instructions.
`JTAG_IC_RESET_ENABLE`	`bit`	Enables the external slice of the IC_RESET TDR; drives the DTP JTAG_IC_RESET_EXT_ENABLE. The SMC slice is always on, and the SEP slice follows SEP.
`JTAG_SMC_DBG_ENABLE`	`bit`	Enables the JTAG2AXI bridge to the SMC debug interface.
`JTAG_STAP_IO_ENABLE`	`bit`	Enables the I/O STAP for chiplet-to-chiplet connectivity.
`JTAG_NUM_EXTRA_STAPS`	`int unsigned`	Number of additional STAPs for local connectivity, 0 to 15 to fit its 4-bit JTAG_CAPS field. The extra STAP port arrays keep one entry when it is 0.
`JTAG_IDCODE_MFR_ID`	`logic [10:0]`	JEDEC manufacturer ID in the DTP IDCODE, and in the SMC CPU and SEP JTAG ID codes.
`JTAG_IDCODE_PART_NUM`	`logic [15:0]`	Part number in the DTP IDCODE, and in the SMC CPU and SEP JTAG ID codes.
`JTAG_IDCODE_SI_REV`	`logic [3:0]`	Silicon revision in the DTP IDCODE, and the version in the SMC CPU and SEP JTAG ID codes.
`JTAG_OCH_VER`	`logic [7:0]`	DTP IP major version reported over JTAG.
`XTRIG_NUM_CTP`	`int unsigned`	External cross-trigger port count, at least 1; forwarded to the DTP XTRIG_NUM_CTP. XTRIG_NUM_CTP + XTRIG_NUM_INT_CT + XtrigSmcIntCtLanes must equal the 26 CT ports of the generated cross-trigger matrix map.
`XTRIG_NUM_INT_CT`	`int unsigned`	SMU-exposed internal CT lane count, 1 to 32; the DTP gets these plus the XtrigSmcIntCtLanes SMC lanes below them.
`XTRIG_NUM_CLK_STOP_REQ`	`int unsigned`	SMU-exposed clock-stop request count, at least 1; the DTP gets these plus the XtrigSmcClkStopLanes SMC lane below them.
`XTRIG_INT_CT_MODE`	`logic [XtrigIntCtModeWidth-1:0]`	Per exposed lane, 0 for pulse sync and 1 for req/ack. Bits at and above XTRIG_NUM_INT_CT are ignored, and the SMC lanes are always pulse sync.
`SMC_OTP_RD_PL_DEPTH`	`logic [1:0]`	DTP JTAG2AXI read pipeline depth toward the SMC OTP, 0 to 3; 0 is a single outstanding read.
`SMC_OTP_WR_PL_DEPTH`	`logic [1:0]`	Write pipeline depth toward the SMC OTP, 0 to 3; it is reported in the JTAG2AXI CAPS only.
`SMC_RD_PL_DEPTH`	`logic [1:0]`	DTP JTAG2AXI read pipeline depth toward the SMC fabric, 0 to 3; 0 is a single outstanding read.
`SMC_WR_PL_DEPTH`	`logic [1:0]`	Write pipeline depth toward the SMC fabric, 0 to 3; it is reported in the JTAG2AXI CAPS only.
`MAX_TRANS`	`int unsigned`	Maximum outstanding AXI-Lite transactions in the SMC pad-ring GPIO demux and each GPIO interface, at least 1; forwarded to the SMC MAX_TRANS.
`SMC_EFUSE_SHIM_SIZE`	`int unsigned`	Size in bytes of the vendor eFuse shim CSR block carved off the base of the smc_external window, greater than 0 and smaller than that window; forwarded to the SMC EFUSE_SHIM_SIZE.
`SEP`	`bit`	1 includes the Secure Execution Processor and the SMU AXI crossbar, and enables the DTP SEP IC_RESET slice and SEP debug STAP. 0 ties the SEP ports off and connects the SMC to the external AXI ports through ID-width converters.
`SEP_EFUSE_SHIM_SIZE`	`int unsigned`	Size in bytes of the eFuse shim CSR window that the SEP diverts from its external aperture to the eFuse wrapper, 1 to 0x1000_0000, the offset of the execute-in-place window; it should cover the shim CSR block. Forwarded to the SEP EFUSE_SHIM_SIZE and unused when SEP is 0.
`SEP_SEC_DISABLE_TOKEN`	`bit [255:0]`	Expected SEP secure-disable token digest, any value. Each bit selects the tap of one revision cell, so a metal ECO can change the digest. Forwarded to the SEP and unused when SEP is 0.
`EXT_TRNG_NUM_AXIS`	`int unsigned`	External TRNG AXI-stream count, one per SEP entropy mux leg; must equal sep_crypto_pkg::SepCryptoEdnEndpointCount (3). Sets the ext_trng_axis_* port widths and is forwarded to the SEP EXT_TRNG_NUM_AXIS.
`SEP_KM_LATCHED_MEM_RDATA`	`bit`	1 when the Key Manager ROM and SRAM macros hold their read data, so the PicoRV32 can look ahead; set it only for such macros. Forwarded to the SEP KM_LATCHED_MEM_RDATA and unused when SEP is 0.
`SEP_ABR_MASKING_EN`	`bit`	Enables Adams Bridge 2-share DOM masking; must match the sep_ip_integration ABR_MASKING_EN. Forwarded to the SEP ABR_MASKING_EN and unused when SEP is 0.
`SEP_ABR_SRAM_LATENCY`	`int unsigned`	Adams Bridge SRAM read latency in cycles, at least 1 and equal to the macro read latency, 1 for the open prim_ram_1r1w. Forwarded to the SEP ABR_SRAM_LATENCY and unused when SEP is 0.

`dtp_ct_mode_t`

DTP per-lane CT mode: the exposed lanes' modes above the zeroed SMC-reserved lanes.

Alias for logic [XtrigIntCtModeWidth+XtrigSmcIntCtLanes-1:0]

`dtp_xtrig_num_int_ct`

DTP internal CT lane count: the exposed lanes plus the SMC-reserved lanes.

Function returning int unsigned

Table 2. `dtp_xtrig_num_int_ct`
Name	Direction	Type	Description
`cfg`	input	`smu_cfg_t`

`dtp_xtrig_num_clk_stop_req`

DTP clock-stop request count: the exposed requests plus the SMC-reserved lane.

Function returning int unsigned

Table 3. `dtp_xtrig_num_clk_stop_req`
Name	Direction	Type	Description
`cfg`	input	`smu_cfg_t`

`jtag_num_extra_stap_ports`

Extra STAP port count: JTAG_NUM_EXTRA_STAPS, but at least one for the tie-off.

Function returning int unsigned

Table 4. `jtag_num_extra_stap_ports`
Name	Direction	Type	Description
`cfg`	input	`smu_cfg_t`

`dtp_xtrig_int_ct_mode`

DTP per-lane CT mode: the exposed lanes' modes above the zeroed SMC-reserved lanes.

Function returning dtp_ct_mode_t

Table 5. `dtp_xtrig_int_ct_mode`
Name	Direction	Type	Description
`cfg`	input	`smu_cfg_t`